1. Field of the Invention
The present invention relates to the field of digital electronics, and more particularly to power consumption of electronic logic devices.
2. Description of the Related Art
Complementary metal oxide semiconductors ("CMOS") have become the dominant integrated circuit technology, largely due to the low power consumption of circuits using such technology. In particular, digital CMOS logic gates have become the building blocks of virtually all of the modem information-related technologies, long-ago overcoming earlier technologies such as NMOS circuits, bipolar circuits, and BiCMOS circuits.
Various CMOS logic families have become well-known to the logic designer. For example, the static CMOS family has become widely used. Static CMOS devices have included both NMOS transistors and PMOS transistors, generally in equal numbers, on a common substrate. Each NMOS transistor has been paired with a PMOS transistor with both transistors in the pair being gated by a common input signal. Each transistor gates its drain terminal to its source terminal voltage when the input signal has a one voltage, and disconnects its drain terminal from its source terminal voltage when the input signal has a different voltage.
Static CMOS technology has had an important power advantage due to the low power consumption of such gates. However, the need to fabricate both NMOS transistors and PMOS transistors has become problematic as devices have become smaller and more densely organized.
To address the need for faster, denser circuits, dynamic CMOS logic technology has emerged. Dynamic logic families such as precharge dynamic logic, differential cascade voltage switch logic, domino logic, complementary pass transistor logic, multiple-output domino logic ("MODL"), latched domino logic, NORA logic, zipper CMOS logic and other dynamic logic families have reduced the number of transistors needed to implement a circuit. Such dynamic logic families have included internal nodes that are precharged to one logic level during one portion (the "precharge" portion) of a clock cycle, and then are selectably discharged during another portion (the "evaluate" portion) of the clock cycle. The discharging is only performed if the input value has a particular value during the evaluate portion.
Although these CMOS logic families differ from one another in many respects, one characteristic that all share is a high capacitance. In all of these CMOS logic families, the inputs to the logic gates are provided to the gate terminals of PMOS transistors or NMOS transistors. Both PMOS transistors and NMOS transistors have relatively high gate-to-substrate capacitances, realized across the oxide layer between the gate terminal and the substrate. The capacitance of such transistors tends to store or consume power.
The gate-to-substrate capacitances within the transistors are only one source of parasitic capacitance within a CMOS logic circuit. The interconnects among the gates generally have greater capacitance than the logic gates themselves. This greater capacitance has largely been caused by the diminution of transistor size. As transistors have become smaller, the interconnects among the logic gates have become the dominant load capacitance for the logic gates. The logic gates themselves, while being extremely small, typically have 1.5 fF/.mu.m of capacitance per gate width. In contrast, the wires have approximately 0.24 fF/.mu.m of wire length, but they may be 1000 .mu.m long, or longer. It is common for the interconnect capacitance to account for 80% or more of the total load capacitance of a logic gate.
It is well known in the electronics industry that the power consumed in charging and discharging a capacitor is equal to the product of the switching frequency, the capacitance, and the square of the voltage being driven onto the capacitor. Although logic gates fabricated of CMOS technologies generally consume far less power than logic gates fabricated of bipolar technologies, as CMOS gates are driven with higher frequency input signals, the power consumed by such logic gates generally increases. At very high frequencies, the low-power advantages of such logic gates all but disappears, and power consumption is quite high. In fact, at very high frequencies, the power consumption of static CMOS logic gates can exceed even that of bipolar junction transistors.
Moreover in a circuit including only static CMOS logic gates, some gates may be left in a particular logic state from one clock cycle to the next. The logic gates that remain in one logic state from one clock cycle to the next consume practically no power, while other logic gates that switch from one state to another consume significant power. Groups of logic gates involved in a particular operation demand greater power of a power supply, while other groups of logic gates that are not involved in a particular operation demand practically no power. When coupled with the potentially high power consumption caused by the parasitic capacitances of wires interconnecting the more active gates, the resulting power imbalance places a heavy burden on power supplies to meet the demands of various portions of a circuit at different times. In addition, overall circuit complexity makes power consumption of the circuit at any particular point in time difficult to calculate. As circuits have become more complex, it has become increasingly unlikely that the logic gates, or portions of logic gates, that may be selected according to the input signal have the same input capacitance. In other words, it has become increasingly unlikely that the output capacitance of the logic gate performing the selection can be independent of the selection itself.
Finally, driving circuits at higher frequencies has created supply impedance problems. The supply loop has a certain inductance, which tends to maintain a relatively constant current in the circuit loop although it impedes altering the amount of current in the circuit loop. Inductance makes abrupt changes in current very difficult, which can cause supply voltage fluctuation. Moreover, the current demand and the change in current, are highly dependant on the nature of the operations being performed. Consequently, compensating for such inductance by designing in on-chip capacitance is very difficult.
The present invention addresses these difficulties with particular applicability to the N-nary logic family. The N-nary logic family supports a variety of signal encodings, including 1-of-4, and is more fully described in the co-pending application, U.S. patent application Ser. No. 09/019,278, filed Feb. 5, 1998, and entitled "Method and Apparatus for Reducing an Integrated Circuit's Power Consumption and Wire to Wire Capacitance Using 1 of N Signals" (hereinafter "N-nary Patent"), which is incorporated by reference into this application. In 1-of-4 encoding, four wires are used to indicate one of four possible values. In contrast, traditional static logic design uses two wires to indicate four values. "Traditional" dual-rail dynamic logic also uses four wires to represent two bits, but the dual-rail scheme always requires two wires to be asserted. In contrast, N-nary logic only requires assertion of one wire. The benefits of N-nary logic over dual-rail dynamic logic, such as reduced power and reduced noise, should be apparent from a reading of The N-nary patent.
All signals in N-nary logic, including 1-of-4, are of the 1-of-N form where N is any integer greater than one. A 1-of-4 signal requires four wires to encode four values (0-3 inclusive), or the equivalent of two bits of information. More than one wire will never be asserted for a 1-of-N signal. Similarly, N-nary logic requires that a high voltage be asserted for all values, even 0.
Any one N-nary gate may comprise multiple inputs and/or outputs. In such a case, a variety of different N-nary encodings may be employed. For instance, consider a gate that comprises two inputs and two outputs, where the inputs are a 1-of-4 signal and a 1-of-2 signal and the outputs comprise a 1-of-4 signal and a 1-of-3 signal. Various variables, including P, Q, R, and S, may be used to describe the encoding for these inputs and outputs. One may say that one input comprises 1-of-P encoding and the other comprises 1-of-Q encoding, wherein P equals two and Q equals four. Similarly, the variables R and S may be used to describe the outputs. One might say that one output comprises 1-of-R encoding and the other output comprises 1-of-S encoding, wherein R equals four and S equals 3. Through the use of these, and other, additional variables, it is possible to describe multiple N-nary signals that comprise a variety of different encodings.